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4.8
Timing Chart and AC Characteristics
4.8.1 Power-on Reset and /or REST Signal Timing
Fig-1 Power-on Reset and RESET signal Timing
4.8.2 I80 type CPU bus write in Timing
VALIDFig-2 Data write-in Timing diagram(i80 bus interface)
Fig –2 Data write-in Timing Diagram
4.8.3 i80 type CPU bus read-out Timing
Fig-3 Dada Read-out Timing Diagram (i80 bus interface)
Tsu(RS)
Min 10ns
TCYC(RD)
Min 10ns
Min 166ns
TWL(RD)
Min 70ns
Th(RS)
Tacc (DATA)
Min 70ns
Twh(/RD)
Min 70nsThw
Min 5ns
RS
/RD
DB0-DB7
Tcyc(/WR)
Min 200ns
Tccl (/WR)
Min 30ns
Th(RS)Min 10ns
Tds(data)Min 30ns
Twh(/WR)
Min 100nsThw(data)
Min 10ns
RS
/WR
DB0-DB7
Tstr(RS)
Min 10ns
0.2V
Toff(Vcc)
Min 100ms
Tr(Vcc)
Max 1ms
4.5V
Twait
Min 500ns
Treset
Min 500ns
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